Prior co-pending U.S. patent application Ser. No. 10/351,276, filed on Jan. 24, 2003, published as U.S. Published Patent Application No. 20030229834, and U.S. patent application Ser. No. 10/750,949, filed on Jan. 5, 2004, published as U.S. Published Patent Application No. 20040148554, have demonstrated techniques to reduce digital test time and test pattern volume, by periodically inserting two-input exclusive-or gates (XOR) between selected pairs of flip-flops in the scan strings, connecting one input of each XOR to the prior flip-flop in the scan string and the other input of each XOR to the data input of the scan string and periodically connecting a flip-flop output of the scan string to a signature register such that the serial shift register scan in and scan out data may be compressed. The prior art describes the need for proper placement of these XOR and tap functions. The present disclosure improves on the work done in the prior art by disclosing a technique whereby more optimal placement of these XOR functions may be determined. The disclosure also presents a modified flip-flop structure, which can serve as both the inserted XOR function or a portion of the signature register.
As shown in FIG. 1, the prior art teaches the conversion of a traditional scan string, comprised of flip-flops 13, which are serially connected in order to be able to shift in test data through the scan string input 14, and shift out test results from the output 15 when testing a digital integrated circuit. The conversion consists of inserting XOR gates 12 periodically throughout the scan string, and periodically tapping off the output of a flip-flop into a checksum function, which is comprised of XOR functions 10 and a Multiple Input Shift Register (MISR) 11, whose output 15 provides a signature of the collected data. In this manner the prior state of the scan string is exclusive-ored with the input data at various points across the scan string to create a pattern with specific values on a subset of the flip-flops, called care-in locations, that are needed to test for specific faulty conditions. In the same fashion, the output results, which are collected from specific points on the scan string, called care-out locations, may be captured to detect the faulty conditions. This technique allows the vast majority of Automatic Test Pattern Generated (ATPG) tests to be performed on the integrated circuit with much less data and in far less shift clock cycles than traditional scan methods. The prior art also presents methods to determine the number of shift cycles and the corresponding input values of these compressed patterns by simulating with variables for the input values, generating a series of equations each consisting of the exclusive-or of the previous captured state in the scan siring with one or more input variables and solving the resulting equations that reside on all of the care-in locations, while determining that sufficient shift cycles have been used to also capture the values on all the care-out locations from the previous pattern.
The current disclosure presents a simple algorithm to ensure that after N cycles shifting into a scan string that contains up to 2N flip-flops, no two flip-flops contain the same equation of input variables, thus optimizing the likelihood of finding a solution to the set of equations at the care-in locations in the fewest number of shifts.
Unfortunately, this solution requires at least half as many XOR functions as there are flip-flops in the scan string to obtain the improved segmentation of the scan-string, so the disclosure also presents a flip-flop with a built-in XOR function and a simple method for converting traditional scan strings into more optimally segmented and tapped scan strings.